Be One Lab Functional Verification Methodology and Flow培訓(xùn)班 |
入學(xué)要求 |
學(xué)員學(xué)習(xí)本課程應(yīng)具備下列基礎(chǔ)知識(shí):
◆ 電路系統(tǒng)的基本概念。 |
班級(jí)規(guī)模及環(huán)境 |
為了保證培訓(xùn)效果,增加互動(dòng)環(huán)節(jié),我們堅(jiān)持小班授課,每期報(bào)名人數(shù)限5人,多余人員安排到下一期進(jìn)行。 |
上課時(shí)間和地點(diǎn) |
上課地點(diǎn):【上海總部】:同濟(jì)大學(xué)(滬西)/星河世紀(jì)廣場(chǎng)(11號(hào)線上海西站) 【深圳分部】:電影大廈(地鐵一號(hào)線大劇院站)/深圳大學(xué)成教院
【北京分部】:北京中山/福鑫大樓 【南京分部】:金港大廈(和燕路) 【武漢分部】:凱盟大廈(新華路)
【成都分部】:四威大廈(泰安里營(yíng)門口路)
近開(kāi)課時(shí)間(周末班/連續(xù)班/晚班): Lab Functional Verification:2025年6月9日........--即將開(kāi)課--............ |
學(xué)時(shí) |
◆課時(shí): 共8天,64學(xué)時(shí)
◆外地學(xué)員:代理安排食宿(需提前預(yù)定)
☆合格學(xué)員免費(fèi)頒發(fā)相關(guān)資格證書,提升您的職業(yè)資質(zhì)
作為早專注于嵌入式培訓(xùn)的專業(yè)機(jī)構(gòu),曙海嵌入式提供的證書得到本行業(yè)的廣泛認(rèn)
可,學(xué)員的能力得到大家的認(rèn)同。
☆合格學(xué)員免費(fèi)推薦工作
★實(shí)驗(yàn)設(shè)備請(qǐng)點(diǎn)擊這兒查看★ |
新優(yōu)惠 |
◆團(tuán)體報(bào)名優(yōu)惠措施:兩人95折優(yōu)惠,三人或三人以上9折優(yōu)惠 。注意:在讀學(xué)生憑學(xué)生證,即使一個(gè)人也優(yōu)惠500元。 |
質(zhì)量保障 |
1、培訓(xùn)過(guò)程中,如有部分內(nèi)容理解不透或消化不好,可免費(fèi)在以后培訓(xùn)班中重聽(tīng);
2、培訓(xùn)結(jié)束后免費(fèi)提供一個(gè)月的技術(shù)支持,充分保證培訓(xùn)后出效果;
3、培訓(xùn)合格學(xué)員可享受免費(fèi)推薦就業(yè)機(jī)會(huì)。 |
Be One Lab Functional Verification Methodology and Flow培訓(xùn)班 |
階段一
-
What is functional verification and what is being verified
Formal Verification,Equivalence Checking,Model checking,
Functional Verification,Test Bench Generation
- Functional Verification Approaches
Black-Box,White-Box,Grey-Box
-
The Verification Process
-
Specification and Test Plan ((Specification->Features->Test cases)
Direct 、Direct-Random and Random Test Case
-
Advanced Verification Methodology
-
System//Chip/Module Level Verification
-
Behavioral Hardware Description Languages
-
Stimulus and Response
Generating complex waveforms,Self-Checking test benches,Complex
Response,Predicting the output
-
How to build reusable test bench
-
Test Bench Acceleration
-
Coverage Analysis in the Design Flow
-
Feature Coverage and Code Coverage (Line Condition Toggle FSM)
Coding Guidelines
Structure,Naming Convention,Comments,Syntax,Debugging
-
Simulation Management
Modeling reset,Writing Good Behavioral Model,Regression Management
-
Assertions Methodology
-
Formal Verification ((Design Rule Check)
-
Vector--based Verification
-
Memory Verification
-
Project Management and Verification Experience
Introduce the useful verification experience that have been
successfully used to produce one-passed ASICs,SoC,board,and
entire systems.
-
Verisity 's Specman e language
-
Verisity 's e VC(e Verification Component)
-
Verisity 's e RM(e Reuse Methodlogy)
|
|